1. Field of the Invention
Embodiments of the invention relate to electronic data transmission, and more particularly, in one or more embodiments, to electronic data transmission over a short channel.
2. Description of the Related Art
In electronic data transmission, various schemes have been used to enhance the accuracy of data transmission over unwanted noise and interference. Typically, electronic data is converted into a signal suitable for transmission over a channel, and is converted back into the original electronic data following reception at the far end.
FIG. 1A illustrates a conventional data transmission system 100 using a CMOS-to-CMOS interface. The system 100 includes a first integrated circuit (IC) 110, a second integrated circuit (IC) 120, and a channel 130 interconnecting the ICs 110, 120. The first IC 110 includes a transmitter 112 including a first transistor T1 and a second transistor T2. The first transistor T1 is a p-type MOS transistor. The second transistor T2 is an n-type MOS transistor. The first transistor T1 includes a source/drain connected to a voltage reference VDD, a drain/source connected to a first node N1, and a gate connected to a second node N2. The second transistor T2 includes a source/drain connected to ground GND, a drain/source connected to the first node N1, and a gate connected to the second node N2. The first node N1 is configured to provide an output signal to the channel 130. The second node N2 is configured to receive a data stream from another component of the first IC 110.
The second IC 120 includes a receiver 122 including a third transistor T3 and a fourth transistor T4. The third transistor T3 is a p-type MOS transistor. The fourth transistor T4 is an n-type MOS transistor. The third transistor T3 includes a source/drain connected to the voltage reference VDD, a drain/source connected to a third node N3, and a gate connected to a fourth N4. The second transistor T2 includes a source/drain connected to ground GND, a drain/source connected to the third node N3, and a gate connected to the fourth node N4. The third node N3 is configured to provide a resulting data stream to another component of the second IC 120. The fourth node N4 is configured to receive a signal from the first IC 110 over channel 130.
During operation, the first to fourth transistors T1-T4 serve as switches. Depending on the logic levels (for example, 1 or 0) of the data stream provided to the second node N2, one of the first transistor T1 or the second transistor T2 is turned on and the other is turned off, thereby pulling up the voltage level of the first node N1 to the voltage of the voltage reference VDD or pulling down the voltage level of the first node N1 to ground GND.
The voltage level of the first node N1 is provided to the fourth node N4 over the channel 130. Depending on the voltage level of the fourth node N4, one of the third transistor T3 or the fourth transistor T4 is turned on and the other is turned off, thereby pulling up the voltage level of the third node N3 to the voltage of the voltage reference VDD or pulling down the voltage level of the third node N3 to ground GND. In this manner, the output from the third node N3 replicates the original data stream received at the second node N2.
FIG. 1B is an eye diagram of a signal at the third node N3 of the receiver 122. Because the third transistor T3 and the fourth transistor T4 are fully on or off in response to a signal transmitted over the channel 130, the voltage swing at the third node N3 is between the voltage levels of the voltage reference VDD and ground GND.